Paper 2000/051 Original: eprint.iacr.org/2000/051 ↗
Reducing the Gate Count of Bitslice DES
Abstract
This paper describes various techniques to reduce the number of logic gates needed to implement the DES S-boxes in bitslice software. Using standard logic gates, an average of 56 gates per S-box was achieved, while an average of 51 was produced when non-standard gates were utilized. This is an improvement over the previous best result, which used an average of 61 non-standard gates.
Metadata
- Available format(s)
PDF- Category
- Implementation
- Publication info
- Preprint.
- History
- 2000-10-09: last updated
- 2000-10-09: published
- Short URL
- https://ia.cr/2000/051
- License
- https://creativecommons.org/licenses/by/4.0/
BibTeX
@misc{cryptoeprint:2000/051,
author = {Matthew Kwan},
title = {Reducing the Gate Count of Bitslice DES},
howpublished = {Cryptology {ePrint} Archive, Paper 2000/051},
year = {2000},
url = {https://eprint.iacr.org/2000/051}
}