Paper 2006/042 Original: eprint.iacr.org/2006/042 ↗
Application of LFSRs for Parallel Sequence Generation in Cryptologic Algorithms
Abstract
We consider the problem of efficiently generating sequences in hardware for use in certain cryptographic algorithms. The conventional method of doing this is to use a counter. We show that sequences generated by linear feedback shift registers (LFSRs) can be tailored to suit the appropriate algorithms. For hardware implementation, this reduces both time and chip area. As a result, we are able to suggest improvements to the design of DES Cracker built by the Electronic Frontier Foundation in 1998; provide an efficient strategy for generating start points in time-memory trade/off attacks; and present an improved parallel hardware implementation of a variant of the counter mode of operation of a block cipher.
Metadata
- Available format(s)
PDF- Category
- Secret-key cryptography
- Publication info
- Preprint.
- History
- 2006-02-28: last updated
- 2006-02-06: published
- Short URL
- https://ia.cr/2006/042
- License
- https://creativecommons.org/licenses/by/4.0/
BibTeX
@misc{cryptoeprint:2006/042,
author = {Sourav Mukhopadhyay and Palash Sarkar},
title = {Application of LFSRs for Parallel Sequence Generation in Cryptologic Algorithms},
howpublished = {Cryptology {ePrint} Archive, Paper 2006/042},
year = {2006},
url = {https://eprint.iacr.org/2006/042}
}