Paper 2006/316 Original: eprint.iacr.org/2006/316 ↗
A Parallelization of ECDSA Resistant to Simple Power Analysis Attacks
Abstract
The Elliptic Curve Digital Signature Algorithm admits a natural parallelization wherein the point multiplication step can be split in two parts and executed in parallel. Further parallelism is achieved by executing a portion of the multiprecision arithmetic operations in parallel with point multiplication. This results in a saving in timing as well as gate count when the two paths are implemented in hardware and software. This article attempts to exploit this parallelism in a typical system context in which a microprocessor is always present though a hardware accelerator is being designed for performance. We discuss some implementation aspects of this design with reference to power analysis attacks. We show how the Montgomery point multiplication and the binary extended gcd algorithms can be adapted to prevent simple power analysis attacks. We implemented our design using a hardware/software parallel architecture. We present the results when the software component is coded on an 8051 architecture and an ARM7TDMI processor.
Metadata
- Available format(s)
PDF- Category
- Implementation
- Publication info
- Preprint.
- History
- 2006-09-22: last updated
- 2006-09-18: published
- Short URL
- https://ia.cr/2006/316
- License
- https://creativecommons.org/licenses/by/4.0/
BibTeX
@misc{cryptoeprint:2006/316,
author = {Sarang Aravamuthan and Viswanatha Rao Thumparthy},
title = {A Parallelization of ECDSA Resistant to Simple Power Analysis Attacks},
howpublished = {Cryptology {ePrint} Archive, Paper 2006/316},
year = {2006},
url = {https://eprint.iacr.org/2006/316}
}