Paper 2011/176 Original: eprint.iacr.org/2011/176 ↗
A FPGA pairing implementation using the Residue Number System
Abstract
Recently, a lot of progresses have been made in software implementations of pairings at the 128-bit security level in large characteristic. In this work, we obtain analogous progresses for hardware implementations. For this, we use the RNS representation of numbers which is especially well suited for pairing computation in a hardware context. A FPGA implementation is proposed, based on an adaptation of Guillermin's architecture which computes a pairing in 1.07 ms. It is 2 times faster than all previous hardware implementations (including ASIC and small characteristic implementations) and almost as fast as best software implementations.
Metadata
- Available format(s)
PDF- Category
- Public-key cryptography
- Publication info
- Preprint.
- History
- 2011-04-08: last updated
- 2011-04-08: published
- Short URL
- https://ia.cr/2011/176
- License
- https://creativecommons.org/licenses/by/4.0/
BibTeX
@misc{cryptoeprint:2011/176,
author = {Sylvain Duquesne and Nicolas Guillermin},
title = {A FPGA pairing implementation using the Residue Number System},
howpublished = {Cryptology {ePrint} Archive, Paper 2011/176},
year = {2011},
url = {https://eprint.iacr.org/2011/176}
}