SHA-3 on ARM11 processors

Peter Schwabe; Bo-Yin Yang; Shang-Yi Yang

Paper 2011/670 Original: eprint.iacr.org/2011/670 ↗

SHA-3 on ARM11 processors

Peter Schwabe

Bo-Yin Yang

Shang-Yi Yang

Abstract

This paper presents high-speed assembly implementations of the 256-bit-output versions of all five SHA-3 finalists and of SHA-256 for the ARM11 family of processors. We report new speed records for all of the six implemented functions. For example our implementation of the round-3 version of JH-256 is 35% faster than the fastest implementation of the round-2 version of JH-256 in eBASH. Scaled with the number of rounds this is more than a 45% improvement.We also improve upon previous assembly implementations for 32-bit ARM processors. For example the implementation of Groestl-256 described in this paper is about 20% faster than the arm32 implementation in eBASH.

Metadata

Available format(s): PDF
Category: Implementation
Publication info: Preprint.
History: 2011-12-16: last updated; 2011-12-16: published
Short URL: https://ia.cr/2011/670
License: https://creativecommons.org/licenses/by/4.0/

BibTeX

@misc{cryptoeprint:2011/670,
      author = {Peter Schwabe and Bo-Yin Yang and Shang-Yi Yang},
      title = {SHA-3 on ARM11 processors},
      howpublished = {Cryptology {ePrint} Archive, Paper 2011/670},
      year = {2011},
      url = {https://eprint.iacr.org/2011/670}
}