Paper 2016/441 Original: eprint.iacr.org/2016/441 ↗
Fault Tolerant Implementations of Delay-based Physically Unclonable Functions on FPGA
Abstract
Recent literature has demonstrated that the security of Physically Unclonable Function (PUF) circuits might be adversely affected by the introduction of faults. In this paper, we propose novel and efficient architectures for a variety of widely used delay-based PUFs which are robust against high precision laser fault attacks proposed by Tajik et al. in FDTC-2015. The proposed architectures can be used to detect run-time modifications in the PUF design due to fault injection. In addition, we propose fault recovery techniques based on either logical reconfiguration or dynamic partial reconfiguration of the PUF design. We validate the robustness of our proposed fault tolerant delay-based PUF designs on Xilinx Artix-7 FPGA platform.
Metadata
- Available format(s)
PDF- Category
- Implementation
- Publication info
- Preprint.
- History
- 2016-05-04: last updated
- 2016-05-04: published
- Short URL
- https://ia.cr/2016/441
- License
- https://creativecommons.org/licenses/by/4.0/
BibTeX
@misc{cryptoeprint:2016/441,
author = {Durga Prasad Sahoo and Sikhar Patranabis and Debdeep Mukhopadhyay and Rajat Subhra Chakraborty},
title = {Fault Tolerant Implementations of Delay-based Physically Unclonable Functions on FPGA},
howpublished = {Cryptology {ePrint} Archive, Paper 2016/441},
year = {2016},
url = {https://eprint.iacr.org/2016/441}
}