Paper 2018/656 Original: eprint.iacr.org/2018/656 ↗
FPGA Cluster based high performance Cryptanalysis framework
Abstract
In this paper a ‘FPGA cluster’ based framework for high performance Cryptanalysis has been proposed. The framework abstracts underlying networked FPGA cluster into a unified acceleration resource. It does so by implementing requested amount of computation kernels (cryptographic modules) and managing efficient distribution of the network band-width between the inter-FPGA and intra-FPGA computation kernels. Further agile methodology for developing such networked computation kernels with use of a high level language (Python) based HDL library and seamless integration with a user space crypt analysis application have been discussed. 40-bit partial key attack over AES256 has been demonstrated as a capability demonstration. Performance higher than clustered CPUs and GPUs at lower costs and power is reported.
Metadata
- Available format(s)
PDF- Category
- Implementation
- Publication info
- Preprint.
- History
- 2018-07-06: last updated
- 2018-07-06: published
- Short URL
- https://ia.cr/2018/656
- License
- https://creativecommons.org/licenses/by/4.0/
BibTeX
@misc{cryptoeprint:2018/656,
author = {Abhishek Bajpai and S V Kulgod},
title = {FPGA Cluster based high performance Cryptanalysis framework},
howpublished = {Cryptology {ePrint} Archive, Paper 2018/656},
year = {2018},
url = {https://eprint.iacr.org/2018/656}
}