Paper 2021/1010 Original: eprint.iacr.org/2021/1010 ↗
Circuit friendly, post-quantum dynamic accumulators from RingSIS with logarithmic prover time
Abstract
Mainstream hash functions such as SHA or BLAKE while generally efficient in their implementations, are not suitable for zero-knowledge boolean or arithmetic circuits due to their reliance on CPU designs. As a candidate hash function that uses only on trivial arithmetics which can be generalized to zeroknowledge circuits, the Ajtai lattice SIS-hasher has been proposed. In this paper we review Micciancio’s R-SIS generalization and argue about it’s circuit complexity, then we show how this R-SIS hasher can be used as a universal dynamic hash accumulator that has constant-time update and revocation complexity, and can be run on 16-bit hardware as well as smart contracts.
Metadata
- Available format(s)
PDF- Category
- Applications
- Publication info
- Preprint.
- History
- 2021-08-06: last updated
- 2021-08-06: published
- Short URL
- https://ia.cr/2021/1010
- License
- https://creativecommons.org/licenses/by/4.0/
BibTeX
@misc{cryptoeprint:2021/1010,
author = {Endre (Silur) Abraham},
title = {Circuit friendly, post-quantum dynamic accumulators from RingSIS with logarithmic prover time},
howpublished = {Cryptology {ePrint} Archive, Paper 2021/1010},
year = {2021},
url = {https://eprint.iacr.org/2021/1010}
}