Paper 2021/693 Original: eprint.iacr.org/2021/693 ↗

Hardware Penetration Testing Knocks Your SoCs Off

Mark Fischer
Fabian Langer
Johannes Mono
Clemens Nasenberg
Nils Albartus
Abstract

Today’s society depends on interconnected electronic devices, which handle various sensitive information. Due to the knowledge needed to develop these devices and the economic advantage of reusable solutions, most of these systems contain Third-Party Intellectual Property (3PIP) cores that might not be trustworthy. If one of these 3PIP cores is vulnerable, the security of the entire device is potentially affected. As a result, sensitive data that is processed by the device can be leaked to an attacker. Competitions like Hack@DAC serve as a playground to develop and examine novel approaches and computer-aided tools that identify security vulnerabilities in System-on-Chip (SoC) Register-Transfer-Level (RTL) designs. In this paper, we present a successful divide and conquer approach to test SoC security which is illustrated by exemplary RTL vulnerabilities in the competition’s SoC design. Additionally, we craft real-world software attacks that exploit these vulnerabilities.

Metadata
Available format(s)
PDF
Category
Applications
Publication info
Preprint.
History
2021-05-28: last updated
2021-05-28: published
Short URL
https://ia.cr/2021/693
License
https://creativecommons.org/licenses/by/4.0/

BibTeX

@misc{cryptoeprint:2021/693,
      author = {Mark Fischer and Fabian Langer and Johannes Mono and Clemens Nasenberg and Nils Albartus},
      title = {Hardware Penetration Testing Knocks Your SoCs Off},
      howpublished = {Cryptology {ePrint} Archive, Paper 2021/693},
      year = {2021},
      url = {https://eprint.iacr.org/2021/693}
}
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