Paper 2022/891 Original: eprint.iacr.org/2022/891 ↗
Secure Physical Design
Abstract
An integrated circuit is subject to a number of attacks including information leakage, side-channel attacks, fault-injection, malicious change, reverse engineering, and piracy. Majority of these attacks take advantage of physical placement and routing of cells and interconnects. Several measures have already been proposed to deal with security issues of the high level functional design and logic synthesis. However, to ensure end-to-end trustworthy IC design flow, it is necessary to have security sign-off during physical design flow. This paper presents a secure physical design roadmap to enable end-to-end trustworthy IC design flow. The paper also discusses utilization of AI/ML to establish security at the layout level. Major research challenges in obtaining a secure physical design are also discussed.
Metadata
- Available format(s)
PDF- Category
- Applications
- Publication info
- Preprint.
- History
- 2022-07-07: last updated
- 2022-07-07: published
- Short URL
- https://ia.cr/2022/891
- License
- https://creativecommons.org/licenses/by/4.0/
BibTeX
@misc{cryptoeprint:2022/891,
author = {Sukanta Dey and Jungmin Park and Nitin Pundir and Dipayan Saha and Amit Mazumder Shuvo and Dhwani Mehta and Navid Asadi and Fahim Rahman and Farimah Farahmandi and Mark Tehranipoor},
title = {Secure Physical Design},
howpublished = {Cryptology {ePrint} Archive, Paper 2022/891},
year = {2022},
url = {https://eprint.iacr.org/2022/891}
}