Paper 2024/670 Original: eprint.iacr.org/2024/670 ↗
Secure Implementation of SRAM PUF for Private Key Generation
Abstract
This paper endeavors to securely implement a Physical Unclonable Function (PUF) for private data generation within Field-Programmable Gate Arrays (FPGAs). SRAM PUFs are commonly utilized due to their use of memory devices for generating secret data, particularly in resource constrained devices. However, their reliance on memory access poses side-channel threats such as data remanence decay and memory-based attacks, and the time required to generate secret data is significant. To address these issues, we propose implementing n cross-coupled inverters in Verilog to generate n secret bits, followed by syndrome for error correction hardcoded in the hardware itself. This approach improves side channel security and reduces time consumption, albeit at the expense of additional area utilization
Metadata
- Available format(s)
PDF- Category
- Implementation
- Publication info
- Preprint.
- History
- 2024-05-02: last updated
- 2024-05-02: published
- Short URL
- https://ia.cr/2024/670
- License
- https://creativecommons.org/licenses/by/4.0/
BibTeX
@misc{cryptoeprint:2024/670,
author = {Raja Adhithan Radhakrishnan},
title = {Secure Implementation of SRAM PUF for Private Key Generation},
howpublished = {Cryptology {ePrint} Archive, Paper 2024/670},
year = {2024},
url = {https://eprint.iacr.org/2024/670}
}