FAEST for Memory-Constrained Devices

Diego F. Aranha; Johan Degn; Jonathan Eilath; Kent Nielsen; Peter Scholl

Paper 2025/1261 Original: eprint.iacr.org/2025/1261 ↗

FAEST for Memory-Constrained Devices

Diego F. Aranha

Johan Degn

Jonathan Eilath

Kent Nielsen

Peter Scholl

Abstract

We introduce a new compact and constant-time implementation of the FAEST v1.1 signature scheme that allows it to run in resource-constrained Arm Cortex-M4 microcontrollers under 190M cycles for signing or verifying at level 1 security. The main technique for reducing the memory footprint is a new abstraction to reuse or recompute VOLEs on demand, which reduces memory consumption by at least an order of magnitude.

Metadata

Available format(s): PDF
Category: Implementation
Publication info: Preprint.
History: 2026-06-29: last updated; 2025-07-08: published
Short URL: https://ia.cr/2025/1261
License: https://creativecommons.org/licenses/by/4.0/

BibTeX

@misc{cryptoeprint:2025/1261,
      author = {Diego F. Aranha and Johan Degn and Jonathan Eilath and Kent Nielsen and Peter Scholl},
      title = {FAEST for Memory-Constrained Devices},
      howpublished = {Cryptology {ePrint} Archive, Paper 2025/1261},
      year = {2025},
      url = {https://eprint.iacr.org/2025/1261}
}